Whitepaper
Optimize Power Distribution Networks for Flat Impedance
This application note from Keysight details a methodology for optimizing Power Distribution Networks (PDNs) to achieve flat impedance across a broad frequency range – crucial for high-speed digital designs like FPGAs. The paper highlights the risks of relying on previous designs or data sheet examples, advocating instead for pre-layout simulation and analysis. It explains how parallel resonance between inductance and capacitance leads to potentially damaging “rogue waves” on the power rail. Using an example targeting 12mΩ impedance for a 5A/60mV FPGA application (Figure 1), it demonstrates how selecting appropriate decoupling capacitors based on system parasitics, rather than generic recommendations, is vital. The core equation provided, C = L / Z<sup>2</sup>, allows for targeted capacitor selection to achieve flat impedance and minimize part count. A complete workflow incorporating pre-layout simulation, post-layout EM analysis, and measurement is recommended to ensure power integrity and reduce EMI/EMC failures.